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| SSG4410 10A, 30V,RDS(ON) 13.5m[ Elektronische Bauelemente N-Channel Enhancement Mode Power Mos.FET RoHS Compliant Product SOP-8 Description The SSG4410 provide the designer with the best Combination of fast switching, ruggedized device design, Ultra low on-resistance and cost-effectiveness. The SOP-8 is universally preferred for all commercial industrial surface mount application and suited for low voltage applications such as DC/DC converters. 0.35 0.49 1.27Typ. 4.80 5.00 0.100.25 3.80 4.00 6.20 5.80 0.25 0.40 0.90 0.19 0.25 45 o 0.375 REF Features * Dynamic dv/dt Rating * Simple drive requirement D 8 D 7 D 6 D 5 0 o 8 o 1.35 1.75 Dimensions in millimeters D * Repetitive avalanche rated * Fast switching 4410SC Date Code G 1 S 2 S 3 S 4 G S Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS@10V Continuous Drain Current, VGS@10V Pulsed Drain Current 1 Symbol VDS VGS ID@TA=25 C ID@TA=70 C IDM PD@TA=25 C o o o Ratings 30 20 10 8 50 2.5 0.02 Unit V V A A A W W/ C o o Total Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Tj, Tstg -55~+150 C Thermal Data Parameter Thermal Resistance Junction-ambient Max. Symbol Rthj-a Ratings 50 o Unit C /W http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 1 of 5 SSG4410 Elektronische Bauelemente 10A, 30V,RDS(ON) 13.5m[ N-Channel Enhancement Mode Power Mos.FET Electrical Characteristics( Tj=25 C Unless otherwise specified) Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Gate Threshold Voltage Gate-Source Leakage Current Drain-Source Leakage Current (Tj=25oC) Drain-Source Leakage Current (Tj=70oC) Static Drain-Source On-Resistance 2 o Symbol BVDSS BVDS/ Tj VGS(th) IGSS IDSS Min. 30 _ Typ. _ Max. _ _ Unit V V/ oC V nA uA uA Test Condition VGS=0V, ID=250uA Reference to 25oC,ID=1mA VDS=VGS, ID=250uA VGS= 20V VDS=30V,VGS=0 VDS=24V,VGS=0 VGS=10V, ID=10A VGS=4.5V, ID=5A 0.037 _ _ _ _ 1.0 _ _ _ _ 3.0 100 1 25 13.5 20 _ _ _ RDS(ON) Qg Qgs Qgd Td(ON) Tr Td(Off) Tf Ciss Coss Crss Gfs 11.5 16.5 20 3 11 7.5 10.2 29 33 955 555 204 20 _ _ _ _ _ _ _ _ _ _ _ m[ Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Forward Transconductance 2 nC ID=10A VDS=15V VGS=5V _ _ _ _ VDD=25V ID=1A nS VGS=5V RG=3.3 [ RD=25 [ _ _ _ pF VGS=0V VDS=15V f=1.0MHz _ _ S VDS=15V, ID=10A Source-Drain Diode Parameter Forward On Voltage 2 Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Symbol VDS Is ISM Min. _ Typ. _ Max. 1.3 Unit V Test Condition IS=1.7A, VGS=0V. VD=VG=0V, VS=1.3V _ _ _ _ 2.3 50 A A Notes: 1.Pulse width limited by safe operating area. 2.Pulse widthO 300us, dutycycleO2%. http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 2 of 5 SSG4410 Elektronische Bauelemente 10A, 30V,RDS(ON) 13.5m[ N-Channel Enhancement Mode Power Mos.FET Characteristics Curve Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature Fig 5. Maximum Drain Current v.s. Case Temperature http://www.SeCoSGmbH.com/ Fig 6. Type Power Dissipation Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 3 of 5 SSG4410 Elektronische Bauelemente 10A, 30V,RDS(ON) 13.5m [ N-Channel Enhancement Mode Power Mos.FET Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics Fig 11. Forward Characteristics of Reverse Diode http://www.SeCoSGmbH.com/ Fig 12. Gate Threshold Voltage v.s. Junction Temperature Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 4 of 5 SSG4410 Elektronische Bauelemente 10A, 30V,RDS(ON) 13.5m [ N-Channel Enhancement Mode Power Mos.FET Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 5 of 5 |
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